This application claims the benefit of Korean Application No. P2001-36969 filed on Jun. 27, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a dual damascene line structure. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for forming a fine pattern in the semiconductor device.
2. Discussion of the Related Art
Various methods for forming a via hole and a trench have been introduced in the method for forming a dual damascene line structure.
A method for forming a via hole after forming a trench and a method for forming a trench after forming a via hole have been suggested as typical methods.
In such methods, a photoresist pattern is formed on the step portion where a via hole and a trench are formed therein. As a result, the photoresist pattern is often found deformed.
A related art method for forming a dual damascene line structure will now be described with reference to the accompanying drawings.
FIGS. 1A to 1D are cross-sectional views illustrating process steps of a related art method for forming a dual damascene line structures. FIGS. 2A to 2D are cross-sectional views illustrating another related art method for forming a dual damascene line structure.
In forming a dual damascene line structure, a via hole may be formed first after forming a trench. Althernatively, a trench may be formed first after forming a via hole.
As shown in FIG. 1A, the method for forming a dual damascene line structure includes selectively etching an insulating layer 2 on a semiconductor substrate 1 to form a trench, burying a metallic layer inside the trench and planarizing the metallic layer to form a lower metallic line 3.
Subsequently, a diffusion barrier layer 4 is deposited on the lower metallic line 3. A low dielectric layer is then deposited on the diffusion barrier layer 4 to form an inter-metal dielectric IMD 5.
Then, after depositing a photoresist on the IMD 5, a photoresist pattern 6 having a via hole pattern is formed by exposure and developing processes so that a portion of the IMD 5 is exposed.
In this case, the photoresist pattern 6 is formed thick enough for forming a deep via hole within the IMD 5 in a later process. Alternatively, the IMD 5 is formed to have a higher etch selectivity than that of the photoresist pattern 6.
Using the photoresist pattern 6 as a mask, the IMD 5 is etched by a plasma dry etching process to form a via hole therein.
As shown in FIG. 1B, after removing the photoresist pattern 6, a polymer remaining within the via hole is removed by a cleaning process.
In addition, as shown in FIG. 1C, after depositing a photoresist on the IMD 5, the IMD 5 is negatively patterned to expose a portion of the IMD 5, thereby forming a photoresist pattern 6a having a trench pattern.
Subsequently, as shown in FIG. 1D, using the photoresist pattern 6a as a mask, the IMD 5 is selectively etched to form a trench.
In this case, a micro-trench shown as portion xe2x80x98Axe2x80x99 is formed inside the trench during the etching process.
Additionally, after depositing a metallic material such as tungsten, which is thick enough to completely bury the via hole and the trench, the metallic material is planarized by a chemical mechanical polishing (CMP) process. Thus, an upper surface of the IMD 5 is exposed, thereby forming a plug (not shown) and an upper metallic line (not shown).
The process of the aforementioned related art method for forming a dual damascene line structure is simple and has an advantage of preventing an increase in a dielectric constant of the IMD 5 through the diffusion barrier layer 4. However, the aforementioned method has a disadvantage in that, in order to form a deep via hole, the photoresist pattern 6 should be thick enough or the IMD 5 should have a higher etch selectivity than that of the photoresist pattern 6.
In addition, removing the polymer that remains within the via hole is difficult, and a micro-trench may be formed in forming the trench.
In FIG. 2A, another related art method of forming a dual damascene line structure includes sequentially depositing a diffusion barrier layer 24, a first IMD 25, an etching stop layer 26, and a second IMD 27 on a semiconductor substrate 21 including a lower metallic line 23 formed within an insulating layer 22.
Then, after depositing a photoresist on the second IMD 27, a photoresist pattern 28 having a trench pattern is formed by exposure and development processes so that a portion of the second IMD 27 is exposed.
As shown in FIG. 2B, using the photoresist pattern 28 as a mask, the second IMD 27 is etched by a plasma dry etching process exposing a portion of the etching stop layer 26 so as to form a trench.
In addition, as shown in FIG. 2C, the photoresist pattern 28 having a trench pattern is removed. A photoresist is once again deposited on the entire surface. Then, the photoresist is patterned by a negative patterning process to expose a portion of the etching stop layer so as to form a photoresist pattern 28a having a via hole pattern.
Subsequently, as shown in FIG. 2D, using the photoresist pattern 28a as a mask, the etching stop layer 26, the first IMD 25, and the diffusion barrier layer 24 are selectively etched exposing a portion of a lower metallic line so as to form a via hole.
Then, after depositing a metallic material such as tungsten, which is thick enough to completely bury the via hole and the trench, the metallic material is polished by a CMP process exposing an upper surface of the second IMD 27 to form a plug (not shown) and an upper metallic line (not shown).
The process of the aforementioned related art method of forming a dual damascene line structure has an advantage of controlling the depth and profile of etching during the trench etching and the via hole etching processes. However, the aforementioned method has a difficulty in controlling the width of the via hole when forming the photoresist pattern for a via hole etching process and an increase in dielectric constant of the IMDs due to the etching stop layer.
As discussed above, the two related art methods for forming a dual damascene line structure have the following problems. When etching a via hole and a trench by using a photoresist pattern as a mask for etching an IMD, it is difficult to form a fine pattern due to the thickness of the photoresist pattern.
This not only results in a difficulty in accurately controlling the size of the trench or the via hole, but also results in a plurality of polymers produced during the etching process of the IMDs.
Accordingly, the present invention is directed to a method for a forming dual damascene line structure that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a method for a forming dual damascene line structure capable of forming a fine pattern, by using two(2) metallic hard masks with completely different etching methods to form a via hole and a trench.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for forming a dual damascene line structure on a substrate includes sequentially depositing an inter-metal dielectric and a first hard mask over the substrate, partially removing the first hard mask to have a positive trench pattern using a first photoresist pattern as a mask, forming a second hard mask having a substantially different etch selectivity from the first hard mask on the partially removed portion of the first hard mask, selectively removing the first hard mask to have a negative via hole pattern using a second photoresist pattern as a mask, partially removing the inter-metal dielectric to have a via hole pattern using the first hard mask as a mask, and forming a trench and a via hole by removing the exposed first hard mask and selectively etching the inter-metal dielectric using the second hard mask.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.